The present invention relates to the fabrication of semiconductor integrated circuits (IC's). More particularly, the present invention relates to methods and apparatuses for etching through an IC's layer stack that includes at least one metallization layer.
In semiconductor IC fabrication, devices such as component transistors are formed on a semiconductor wafer or substrate, which is typically made of silicon. Metallic interconnect lines, which are etched from a metallization layer disposed above the wafer, are then employed to couple the devices together to form a desired circuit. To facilitate discussion, FIG. 1 illustrates a cross-section view of a layer stack 20, representing the layers formed during the fabrication of a typical semiconductor IC. It should be noted that other additional layers above, below, or between the layers shown may be present. Further, not all of the illustrated layers need necessarily be present and some or all may be substituted by a variety of different layers.
At the bottom of layer stack 20, there is shown a wafer 100. An oxide layer 102 which is typically a silicon dioxide (SiO.sub.2) is shown formed over the surface of wafer 100. A barrier layer 104, typically formed of Ti, TiW, TiN or other suitable barrier materials, may be disposed between oxide layer 102 and a subsequently deposited metallization layer 106. Barrier layer 104, when provided, functions to substantially prevent diffusion of silicon atoms from oxide layer 102 and into the metallization layer.
Metallization layer 106 typically includes aluminum, copper or one or more of a variety of known aluminum alloys such as Al-Cu, Al-Si, and Al-Cu-Si. The remaining two layers of FIG. 1 include an anti-reflective coating (ARC) layer 108 that is formed over metallization layer 106, and an overlaying photoresist (PR) layer 110 formed over ARC layer 108. As is well known in the art, ARC layer 108 is typically composed of Ti, TiN or TiW. Generally speaking, ARC layer 108 is useful in preventing light used in photolithography processes from reflecting and scattering off of the metallization layer 106 surface, and may, in some cases, inhibit hillock growth.
As mentioned above, photoresist layer 110 represents a layer of conventional resist material that may be patterned using patterned reticles and a stepper that passes ultra-violet rays onto the surface of photoresist layer 110. The layers of layer stack 20 are readily recognizable to those skilled in the art and may be formed using any number of known deposition processes, including chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and physical vapor deposition (PVD) such as sputtering.
To create the aforementioned metallic interconnect lines, the PR layer 110 is patterned with a suitable photolithography technique, and subsequently the exposed metal film(s) are etched. By way of example, one such photolithography technique involves the patterning of photoresist layer 110 by exposing the photoresist material in a contact or stepper photolithography apparatus, and the development of the photoresist material to form a patterned mask that exposes certain portions of the underlying metallization layer 108. In this manner, subsequent etchants may be used to etch away portions of the underlying metallization layers that are not covered by the remaining photoresist mask. Accordingly, the remaining metallization material will form a plurality of interconnect lines that are consistent with a selected functional circuit pattern.
For illustration purposes, FIG. 2 shows a cross-section view of layer stack 20 of FIG. 1 after conventional etching is completed. In this example, the metallic interconnect lines are represented by the unetched portions of metallization layer 106. To achieve greater circuit density, modern IC circuits are scaled with increasingly narrower design rules. As a result, the feature sizes, i.e., the width of the interconnect lines and spacings (e.g., trenches) between adjacent interconnect lines, have steadily decreased. By way of example, while a line width of approximately 0.8 microns (.mu.m) is considered acceptable in a 4 megabit (Mb) dynamic random access memory (DRAM) IC, 256 Mb DRAM IC's generally employ interconnect lines that are about 0.25 microns wide, or even thinner.
As feature sizes continue to shrink, it has become increasingly difficult to achieve a uniform etch rate across the surface of a selected wafer. Typically, the etch rate in narrow spacings is slower than that in the wider, open field regions. This phenomenon is referred to as "etch rate loading," and is believed to be a consequence of "microloading" and "aspect ratio dependent etching" (ARDE). Mircroloading refers primarily to a situation wherein the etch rate is less in areas where there is a high density of line spacings relative to the etch rate of identically sized trenches located in a less dense area.
ARDE, on the other hand, refers to the variation in the etch rate uniformity due to the variations in the height of the photoresist layer divided by a width of a selected trench (i.e., aspect ratio.apprxeq.height/width). A variety of techniques may be used to reduce ARDE which may include decreasing the height of the photoresist masking layer or other masking materials. Unfortunately, when the height of the photoresist masking layer is decreased, many commonly used etching chemistries rapidly etch through this masking layer leaving sensitive underlying layers regions exposed for inadvertent etching. Further, the ARDE problem tends to be even more prominent when trench width dimensions are decreased.
As a result of these etch rate variations, by the time metal etching is complete in areas having a slow etch rate (e.g., narrower space regions), overetching, i.e., the inadvertent removal of materials from underlying layers, may have already occurred in areas having a higher etch rate (e.g., open field regions).
With reference to FIG. 2, area 120 represents an open field region where the metallization layer is extensively overetched (by distance d1), area 121 represents an overetched region (by distance d2), and area 122 represents an underetched area where the metallization is extensively underetched (by distance d3). If the etch rate variations are sufficiently large, certain semiconductor devices may not be etched to target layers without destroying sensitive layers with extensive overetching. By way of example, the metal layer in area 122 will not be sufficiently etched before layers in the open field regions 120 are damaged. Thus, large etch rate variations may cause undue overetching and excessive oxide loss in area 120, rendering the wafer undergoing processing unsuitable for use in further IC fabrication.
In view of the foregoing, what is needed are improved methods and apparatuses for reducing etch rate loading when the etching layer stack. Further, there is a need for methods and apparatuses that allow for the reduction of photoresist aspect ratios through the use of etching chemistries that are highly selective to photoresist.